To quickly process instructions in a single processor having one operation unit, the execution cycle of the processor should be accelerated. Based on current technology, however, the clock cycle of a microprocessor is near the clock cycle of supercomputers, and thus, the process of acceleration of the execution cycle is limited. Thus, a technique for processing several instructions at a time is needed to improve the execution speed of instructions. Due to the increase in demands for improvement of performance for computer processing, the computer structures have been developed that enable simultaneous execution of multiple instructions.
For example, FIG. 1 is a block diagram illustrating the structure of a conventional very long instruction word (VLIW) processor 100. The VLIW processor 100 schedules a plurality of instructions using a compiler so that several instructions are simultaneously executed. The VLIW processor 100 includes a plurality of functional units (FUs) 141-147, which are controlled periodically by a VLIW instruction and are connected in parallel with one another. The VLIW processor 100 includes issue slots 121-127, which specify specific operations that are performed on the FUs 141-147, respectively, and a register file 190, which transfers operands to the FUs 141-147 and stores the results of operations of the FUs 141-147.
A VLIW instruction used in the VLIW processor 100 comprises a number n of sub-instructions. In a case where a maximum number of VLIW sub-instructions is m, the number of VLIW sub-instructions is represented as 0<n≦m. In a case where the total number of FUs is k, the number (k) of FUs for processing the VLIW sub-instructions is equal to or greater than m, that is, k≧m.
In general, there are two methods for determining FUs on which each sub-instruction should be executed. A first method is to constitute such a VLIW as to have a maximum number (that is, m) of sub-instructions, which is the same as the total number (that is, k) of FUs, as shown in FIG. 1. In this case, sub-instructions to be transmitted to each FU are determined by positions of sub-instructions constituting a VLIW instruction. For this purpose, the number (that is, n) of the sub-instructions should always have the value of m. Thus, the first method may result in program codes being wasted. A second method is to encode information on FUs in sub-instructions. This method is typically used to solve the problem occurring in the first method.
FIG. 2 illustrates a case where information on FUs is encoded together in the sub-instructions. Referring to FIG. 2, respective information, as to which FU a corresponding sub-instruction is to be used for, is encoded in each of sub-instructions 131-136. However, according to the second method, as the number (that is, k) of FUs increases, the length of sub-instructions increases, and the logic for decoding the information on FUs becomes complicated.